1. Technical Field
The disclosure relates generally to integrated circuitry, and more particularly, to methods of forming a vertical spacer and a related transistor.
2. Background Art
Spacers are common structures in complementary metal-oxide semiconductor (CMOS) processing provided to protect one structure from processing done to an adjacent structure. Illustrative types of CMOS devices in which protective spacers must be used include fin field effect transistors (FinFETs), multi-gated field effect transistors (MUGFETs) or a tri-gate device. A FinFET, for example, structurally includes, among other things, a gate that extends over and along a portion of each sidewall of a thin, vertical, silicon “fin.” In FinFETS, a spacer is required for blocking implants at the gate edge and preventing silicide shorts to the gate. Conventional planar CMOS spacer processing presents a number of problems relative to the fin. In particular, if conventional spacer processes are used, fin erosion during spacer etch, is a potential problem. When the fin needs to be exceptionally thin, any additional etching can prevent attainment of the desired fin size. Another challenge is formation of a spacer having a uniform thickness such that the part of the fin not adjacent to the gate can be exposed to a uniform implantation. In conventional spacer etching, as shown in FIG. 1 in an illustrative finFET setting, a spacer 10 formed on a gate 12 over a fin 14 tends to have a narrower top than a bottom, resulting in non-uniform implantation of adjacent source-drain regions 16 in fin 14. Similar problems exist relative to other CMOS devices such as MUGFETs.